HPCAN

High Performance Computing Architectures & Networks

Books and Book Chapters

1.        H. Sarbazi-Azad (Editor), Dark silicon aware design of future processors, in Advances in Computers, Elsevier, in progress.

2.        H. Sarbazi-Azad (Editor), Advances in GPU research and practice, Elsevier Science, Morgan Kaufmann Publishing Co., 2017, ISBN: 978-0-128-03788-1.

3.        M.H. Samavatian, M. Arjomand, R. Bahizadeh, H. Sarbazi-Azad, Architecting the last-level cache for GPUs using STT-RAM nonvolatile memory, Chapter 20 in Advances in GPU research and practice, Elsevier & Morgan Kaufmann, 2017, ISBN: 978-0-12-803738-6.

4.        P. Zardoshti, F. Khunjush, H. Sarbazi-Azad, Adaptive sparse matrix representation for efficient matrix-vector multiplication, Chapter 14 in Advances in GPU research and practice, Elsevier & Morgan Kaufmann, 2017, ISBN: 978-0-12-803738-6.

5.        A. Hurson, H. Sarbazi-Azad (Editors), Energy efficiency in data centers, in Advances in Computers, Vol. 100, Elsevier, 2016.

1.        H. Sarbazi-Azad, A. Zomaya (Editors), Large-scale network-centric distributed systems, Wiley Book Series on Parallel and Distributed Computing, 2013, ISBN: 978-0-470-93688-7.

2.        R. Jabbarvand, Mehdi Modarressi, H. Sarbazi-Azad, Fault-tolerant routing algorithms, Chapter 4 in Networks on-Chip, Springer, 2013.

3.        M. Modarressi, H. Sarbazi-Azad, A reconfigurable on-chip interconnection network for large multicore systems, Chapter 1 in Large scale network centric distributed systems, By H. Sarbazi-Azad, A. Zomaya (Editors), Wiley Book Series on Parallel and Distributed Computing, 2013, ISBN: 978-0-470-93688-7.

4.        A. Nayebi, H. Sarbazi-Azad, Mobility effects in wirelss mobile networks, Chapter 8, Large scale network centric distributed systems, By H. Sarbazi-Azad, A. Zomaya (Editors), Wiley Book Series on Parallel and Distributed Computing, 2013, ISBN: 978-0-470-93688-7.

5.        M. Modarressi, H. Sarbazi-Azad, A high-performance and low-power on-chip network with reconfigurable topology, Chapter13, Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication, By Jih-Sheng Shen and Pao-Ann Hsiung (Editors), IGI Global Publisher, 2010, ISBN: 978-1-61520-807-4.

6.        R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, Shuffle-exchange mesh topology for networks-on-chip, Chapter 5 in Parallel and Distributed Computing, IN-TECH Publishers, Austria, 2010, ISBN: 978-3-902613-45-5.

7.        R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, A novel de Bruijn based mesh topology for Networks-on-Chip, Chapter 16 in VLSI Design, IN-TECH Publishers, Austria, 2010, ISBN 978-3-902613-50-9.

8.        H. Hashemi, H. Sarbazi-Azad, Performance modeling and evaluation of opto-electronic OTIS cubes, Chapter 4, Performance Evaluation of Parallel, Distributed and Emergent Systems, By G. Min and M. Ould-khaoua (Editors), Nova Science Publishers, 2006, ISBN: 1-59454-817-X, pp. 83-107.

9.        A. Khonsari, H. Sarbazi-Azad, M. Ould-Khaoua, A performance model of true fully adaptive routing in hypercubes, Chapter 16, High Performance Computing Systems and Applications, R. D. Kent, T. W. Sands (Editors), Kluwer Academic Publishers, 2003, ISBN: 1-4020-7389-5.

Editorials in Journals

1.        H. Asadi, P. Ienne, H. Sarbazi-Azad, Architecture of future many core systems, Elsevierís Microprocessors and Microsystems, Vol.46, pp.264-273, 2016.

2.        H. Sarbazi-Azad, N. Bagherzadeh, M. Ebrahimi, M. Daneshtalab, On-chip parallel and network-based systems, Editorial notes, Elsevierís Computers and Electrical Engineering, Vol.51, No.2, pp.118-120, 2016.

3.        H. Asadi, P. Ienne, H. Sarbazi-Azad, Emerging memory technologies, IEEE Transactions on Computers, 65(4):1006-1009, 2016.

4.        H. Sarbazi-Azad, N. Bagherzadeh, G. Jaberipour, Multicore architectures, Editorial notes, Elsevierís Journal of Supercomputing, Vol.71, No.8, pp.2783-2786, 2015.

5.        M. Daneshtalab, H. Sarbazi-Azad, N. Bagherzadeh, On-chip parallel and network-based systems, Editorial notes, Integration: The VLSI Journal, Vol.50, pp.137-138, 2015.

6.        M. Daneshtalab, H. Sarbazi-Azad, N. Bagherzadeh, On-chip parallel and network-based systems, Editorial notes, Computing, Vol.97, No.6, pp.539-541, 2015.

7.        D. GŲhringer, H. Sarbazi-Azad, R. Stotzka, Network-on-chips and memories for multicore architectures, Editorial notes, Elsevierís Microprocessors and Microsystems, Vol.38, No.4, pp.253-254, 2014.

8.        H. Sarbazi-Azad, N. Bagherzadeh, Multicore computing systems: architecture, programming tools, and applications, Editorial notes, Journal of Computer and System Sciences, Vol.79, No.4, pp.403-405, 2013.

9.        N. Bagherzadeh,H. Sarbazi-Azad, High-performance computer architecture and systems: design and performance, Editorial notes, IET Computers and Digital Techniques, Vol.6, No.5, pp.257-258, 2012.

10.     H. Sarbazi-Azad, N. Bagherzadeh, On-chip parallel and network-based systems, Editorial notes, Elsevierís Microprocessors and Microsystems, Vol.36, No.7, pp.529-530, 2012.

11.     N. Bagherzadeh, H. Sarbazi-Azad, On-chip Parallel and Network-based Systems, Editorial notes, Journal of Systems Architecture, Vol. 57, No.1, pp. 1-3, 2011.

12.     H. Sarbazi-Azad, A.R. Shahrabi, H. Beigy, Network-based high performance computing, Editorial notes, Springerís Supercomputing journal, Vol. 53, No. 1, pp. 1-4, 2010.

13.     H. Sarbazi-Azad, L. Mackenzie, Advances in computing systems science and engineering, Editorial notes, Elsevierís Computers and Electrical Engineering, Vol. 36, pp. 803-1020, Issue 5, 2010.

14.     H. Sarbazi-Azad, L. Mackenzie, Network-based computing, Editorial notes, Elsevierís Journal of Computer and System Sciences, Vol.73, pp. 1119-1120, 2007.

15.     H. Sarbazi-Azad, M. Ould-Khaoua, A. Zomaya, Performance evaluation of networks for parallel, cluster, and grid computing, Editorial notes, Elsevierís Parallel Computing, Vol.32, No. 11 and 12, pp.775-776, 2006.

16.     H. Sarbazi-Azad, M. Ould-Khaoua, A. Zomaya, Design and performance of networks for super-, cluster-, and grid-computing: Part II, Editorial notes, Elsevierís Journal of Parallel and Distributed Computing, Vol.65, No.10, pp. 1301-1304, 2005.

17.     H. Sarbazi-Azad, M. Ould-Khaoua, A. Zomaya, Design and performance of networks for super-, cluster-, and grid-computing: Part I, Editorial notes, Elsevierís Journal of Parallel and Distributed Computing, Vol.65, No.9, pp. 1119-1122, 2005.

18.     M. Ould-Khaoua, H. Sarbazi-Azad, M. S. Obaidat, Performance modeling and evaluation of high-performance parallel and distributed systems, Editorial notes, Elsevierís Performance Evaluation: An International Journal, Vol. 60, No.1, 2, 3, and 4, pp. 1-4, 2005.

Selected Journal Papers

1.        M. Jalili, H. Sarbazi-Azad, Endurance-aware security enhancement in non-volatile memories using compression and selective encryption, IEEE Transaction on Computers, to appear.

2.        D. Rahmati, H. Sarbazi-Azad, Classified round robin: a simple prioritized arbitration to equip best effort NoCs with effective hard QoS, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear.

3.        M. Hoveida, F. Agha-aliakbari, M. Arjomand, H. Sarbazi-Azad, Efficient mapping of applications for future chip-multiprocessors in dark-silicon era, ACM Transactions on Design Automation of Electronic Systems, to appear.

4.        M. Bakhshalipour, P. Lotfi-Kamran, H. Sarbazi-Azad, An efficient temporal data prefetcher for L1 caches, IEEE Computer Architecture Letters, to appear.

5.        M. Hosseinzadeh, M. Arjomand, H. Sarbazi-Azad, SPCM: The striped phase change memory, ACM Transactions on Computer Architecture and Code Optimization, 12(4):38-52, 2016.

6.        P. Lotfi-Kamran, M. Modarressi, H. Sarbazi-Azad, An efficient hybrid-switched network-on-chip for chip multiprocessors, IEEE Transaction on Computers, 65(5):1656-1662, 2016.

7.        A. Tavakkol, M. Arjomand, H. Sarbazi-Azad, Unleashing the potentials of dynamism for page allocation strategies in SSDs, ACM Transactions on Modeling and Performance Evaluation of Computing Systems, Vol.12, No.4, pp.38-52, 2016.

8.        A. Tavakkol, P. Mehrvarzy, H. Sarbazi-Azad, TBM: Twin block management policy to enhance the utilization of plane-level parallelism in SSDs, IEEE Computer Architecture Letters, to appear. (DOI: 10.1109/LCA.2015.2461162)

9.        M. Tarihi, H. Asadi, M. Arjomand, H. Sarbazi-Azad, A hybrid non-volatile cache design for solid-state drives using comprehensive I/O characterization, IEEE Transaction on Computers, Vol.65, No.6, pp.1678-1691, 2016.

10.     M.R. Jokar, M. Arjomand, H. Sarbazi-Azad, Sequoia: A high-endurance NVM-based cache architecture, IEEE Transactions on VLSI Systems, Vol.24, No.3, pp.954-967, 2016.

11.     A. Sheshboloki, M. Zarei, H. Sarbazi-Azad, The role of leadership in synchronization of directed complex networks, Journal of Statistical Mechanics Theory and Experiment, No.10, pp.2-17, 2015.

12.     A. Sheshboloki, M. Zarei, H. Sarbazi-Azad, Are feedback loops destructive to synchronization?, Europhysics Letters, Vol.111, No.4, pp.3-9, 2015.

13.     M. H. Samavatian, M. Arjomand, R. Bashizadeh, H. Sarbazi-Azad, Architecting the last-level cache for GPUs using STT-RAM technology, ACM Transactions on Design Automation of Electronic Systems, Vol.20, No.4, pp.55-73, 2015.

14.     M. Asadinia, M. Arjomand, H. Sarbazi-Azad, Variable resistance spectrum assignment in phase change memory systems, IEEE Transactions on VLSI Systems, Vol.23, No.11, pp.2657-2670, 2015.

15.     M. Asadinia, M. Arjomand, H. Sarbazi-Azad, Prolonging lifetime of PCM-based main memories through on-demand page pairing, ACM Transactions on Design Automation of Electronic Systems, Vol.20, No.2, pp.23-37, 2015.

16.     M. Tarihi, H. Asadi, H. Sarbazi-Azad, DiskAccel: accelerating disk-based experiments by representative sampling, ACM Performance Evaluation Review, Vol.42, No.1, pp.551-552, 2014.

17.     A. Tavakkol, M. Arjomand, H. Sarbazi-Azad, Unleashing the potentials of dynamism for page allocation strategies in SSDs, ACM Performance Evaluation Review, Vol.42, No.1, pp.551-552, 2014.

18.     A. Tavakkol, M. Arjomand, H. Sarbazi-Azad, NoSSD: A scalable and high-performance communication design paradigm for SSDs, IEEE Computer Architecture Letters, Vol.12, No.1, pp.5-8, 2013.

19.     C. Seiculescu, D. Rahmati, M. Srinivasan, H. Sarbazi-Azad, L. Benini, G. De Micheli, Designing best effort networks-on-chip to meet hard latency constraints, ACM Transactions on Embedded Computing Systems, Vol.12, No.4, pp.108-122, 2013.

20.     D. Rahmati, S. Murali, L. Benini, F. Angiolini, G. De Micheli, H. Sarbazi-Azad, Computing accurate performance bounds for best effort networks-on-chip, IEEE Transactions on Computers, Vol.62, No.3, pp.452-467, 2013.

21.     M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, Application-aware topology reconfiguration for on-chip networks, IEEE Transactions on VLSI Systems, Vol.19, No.11, pp.2010-2022 , 2011.

22.     A. Nayebi, G. Karlsson, H. Sarbazi-Azad, Evaluation and design of beaconing in mobile wireless networks, Ad Hoc Networks, Vol.9, No.3, pp.368-386, 2011.

23.     M. Arjomand, H. Sarbazi-Azad, Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes, IEEE Transactions on Computer Aided Design for Digital Systems, Vol.29, No.10, pp.1558-1571, 2010.

24.     M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, Virtual point-to-point connections for NoCs, IEEE Transactions on Computer Aided Design for Digital Systems, Vol.29, No.6, pp.855-868, 2010.

25.     R. Moraveji, P. Moinzadeh, H. Sarbazi-Azad, A. Zomaya, Multi-spanning tree zone-ordered label-based routing algorithms for irregular networks, IEEE Transactions on Parallel and Distributed Systems, Vol.22, No.5, pp.817-832, 2011 .

26.     N. Imani, H. Sarbazi-Azad, A. Zomaya, P. Moinzadeh, Detecting threats in star graphs, IEEE Transactions on Parallel and Distributed Systems, Vol.20, No.4, pp. 474-483, 2009.

27.     N. Imani, H. Sarbazi-Azad, S.G. Akl, Some topological properties of star graphs: the surface area and volume, Discrete Mathematics, Vol.309, pp.560-569, 2009.

28.     H. Sarbazi-Azad, M. Ould-Khaoua, L. M. Mackenzie, Analytical modelling of wormhole-routed k-ary n-cubes in the presence of hot-spot traffic, IEEE Transactions on Computers, Vol. 50, No. 7, pp. 623-634, 2001.

29.     H. Sarbazi-Azad, M. Ould-Khaoua, L.M. Mackenzie, An accurate analytical model of adaptive wormhole routing in k-ary n-cube interconnection networks, Performance Evaluation, Vol. 43, No. 2-3, pp. 165-179, 2001.

30.     M. Ould-Khaoua, H. Sarbazi-Azad, An analytical model of adaptive wormhole routing in hypercubes in the presence of hotspot traffic, IEEE Transactions on Parallel and Distributed System, Vol. 12, No.3, pp. 283-292, 2001.

 

Selected Conference Papers

1.        M. Sadrosadati, A.H. Mirhosseini, S. Roozkhosh, H. Bakhishi, H. Sarbazi-Azad, Effective cache bank placement for GPUs, International Conference on Design, Automation and Test in Europe (DATE 2017), 27-31 March 2017, Lausanne, Switzerland.

2.        P. Lotfi-Kamran, M. Modarressi, H. Sarbazi-Azad, Near-ideal networks-on-chip for servers, The 23rd IEEE Symposium on High Performance Computer Architecture (HPCA2017), 4-8 February 2017, Austin, TX, USA.

3.        H. Aghilinasab, M. Sadrosadati, M. Samavatian, H. Sarbazi-Azad,  Reducing power consumption of GPGPUs through instruction reordering, International Symposium on Low Power Electronics and Design (ISLPED 2016), 8-10 August 2016, San Francisco, CA, USA.

4.        M. Asadinia, M. Jalili, H. Sarbazi-Azad, BLESS: a simple and efficient scheme for prolonging PCM lifetime, 53rd Design Automation Conference (DAC2016), 1-5 June 2016, Austin, TX, USA.

5.        M. Jalili, H. Sarbazi-Azad, Captopril: reducing the pressure of bit flips on hot locations in non-volatile main memories, International Conference on Design, Automation and Test in Europe (DATE 2016), 14-18 March 2016, Dresden, Germany.

6.        M. Sadrosadati, A. Mirhosseini, H. Aghilinasab, H. Sarbazi-Azad, An efficient DVS scheme for on-chip networks using reconfigurable virtual channel allocators, International Symposium on Low Power Electronics and Design (ISLPED 2015), 22-24 July 2015, Rome, Italy.

7.        A. Mirhosseini, M. Sadrosadati, A. Fakhrzadehgany, M. Modarressi, and H. Sarbazi-Azad, An energy-efficient virtual channel power-gating mechanism for on-chip networks, International Conference on Design, Automation and Test in Europe (DATE 2015), 9-13 March 2015, Grenoble, France.

8.        M. Tarihi, H. Asadi, H. Sarbazi-Azad, DiskAccel: accelerating disk-based experiments by representative sampling, ACM SIGMETRICS, 15-19 June 2015, Portland, Oregon, USA.

9.        A. Tavakkol, M. Arjomand, H. Sarbazi-Azad, Design for scalability in enterprise SSDs, The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT2014), 24-27 August 2014, Edmonton, Alberta, Canada.

10.     M. Hoseinzadeh, M. Arjomand, H. Sarbazi-Azad, Reducing access latency of MLC PCMs, 41st ACM/IEEE International Symposium on Computer Architecture (ISCA2014), 14-18 June 2014, Minneapolis, MN, USA.

11.     M. Jalili, M. Arjomand, H. Sarbazi-Azad, A reliable 3D MLC PCM architecture with resistance drift predictor, 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN2014), 23-26 June 2014, Atlanta, GA, USA.

12.     A. Tavakkol, M. Arjomand, H. Sarbazi-Azad, Unleashing the potentials of dynamism for page allocation strategies in SSDs, ACM SIGMETRICS, 16-20 June 2014, Austin, TX, USA.

13.     M. Samavatian, M. Abbasitabar, M. Arjomand, H. Sarbazi-Azad, Fast and low-power STT-RAM last level cache for GPGPUs, 51st Design Automation Conference (DAC2014), 1-5 June 2012, San Francisco, CA, USA.

14.     M. Asadinia, M. Arjomand, H. Sarbazi-Azad, OD3P: on-demand page paired PCM, 51st Design Automation Conference (DAC2014), 1-5 June 2012, San Francisco, CA, USA.

15.     M. Arjomand, H. Sarbazi-Azad, A. Jadidi, M. Rezaei, Relaxing writes in non-volatile processor cache using frequent value locality, 49th Design Automation Conference (DAC), 3-7 June 2012, San Francisco, CA, USA.

16.     M. Arjomand, A. Jadidi, A. Shafiee, H. Sarbazi-Azad, A morphable phase change memory architecture considering frequent zero values, International Conference on Computer Design (ICCD), 9-12 October 2011, Amherst, MA, USA.

17.     R. Jabbarvand, M. Modarressi, H. Sarbazi-Azad, A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults, International Conference on Computer Design (ICCD), 9-12 October 2011, Amherst, MA, USA.

18.     A. Shafiee, M. Zolghadr, M. Arjomand, H. Sarbazi-Azad, Application-aware deadlock-free oblivious routing based on extended turn-model, International Conference on Computer-Aided Design (ICCAD),  6-10 November 2011, San Jose, California, USA.

19.     A. Jadidi, M. Arjomand, H. Sarbazi-Azad, High-endurance and performance-efficient design of hybrid cache architecture through adaptive line replacement, International Symposium on Low Power Electronics and Design (ISLPED), 1-3 August 2011, Fukuoka, Japan.

20.     M. Asadinia, M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, Supporting non-contiguous processor allocation in CMPs using virtual point-to-point links, Design Automation and Test in Europe (DATE), 14-18 March 2011, Grenoble, France.

21.     M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, An efficient dynamically reconfigurable on-chip network architecture, 47th Design Automation Conference (DAC), 13-18 June 2010, Anaheim, California.

22.     D. Rahmati, S. Murali, L. Benini, F. Angiolini, G. De Micheli, H. Sarbazi-Azad, A method for calculating hard QoS guarantees for networks-on-Chip, IEEE/ACM The International Conference on Computer-Aided Design (ICCAD), 2-5 November 2009, San Jose, CA, USA.

23.     H. Sadeghi, H. Sarbazi-Azad, H.R. Zarandi, Power-aware branch target prediction using a new BTB architecture, The 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 12-14 October 2009, Florianapolis, Brazil .

24.     M. Modarressi, H. Sarbazi-Azad, A. Tavakol, Performance and power efficient on-chip communication using adaptive virtual point-to-point connections, ACM/IEEE Symposium on Networks-on-Chip (NOCS), 10-13 May 2009, San Diego, CA, USA.

25.     M. Arjomand, H. Sarbazi-Azad, A comprehensive power-performance model for NoCs with multi-flit channel buffers, 23rd International Conference on Supercomputing (ICS), 8-12 June 2009, New York, USA.

26.     M. Modarressi, H. Sarbazi-Azad, A hybrid packet-switched and circuit-switched on-chip network based on spatial-division multiplexing, Design, Automation and Test in Europe (DATE), 20-24 April 2009, Nice, France.

27.     M. Modarressi, H. Sarbazi-Azad, A. Tavakol, Virtual point-to-point links in packet switched NoCs, IEEE International Symposium on VLSI (IEEE ISVLSI2008), 2008, France.

28.     R. Sabbaghi, H. Sarbazi-Azad, The 2D DBM: an attractive alternative to the simple 2D mesh topology for on-chip networks, 26th IEEE International Conference on Computer Design (ICCD), October 12-15, 2008, Lake Tahoe, California, USA.

29.     M. Modarressi, H. Sarbazi-Azad, Power-aware mapping for reconfigurable NoC architectures, IEEE International Conference on Computer Design (IEEE ICCD), 7-10 October 2007, Lake Tahoe, CA, USA.

30.     N. Imani, H. Sarbazi-Azad, A. Zomaya, Capturing an intruder in product networks, 13th Annual IEEE International Conference on High Performance Computing (IEEE HiPCí2006), December 18-21, 2006, Bangalore, India, pp.193-204.

31.     D. Rahmati, A. Eslami, S. Hessabi, H. Sarbazi-Azad, A performance and power analysis of WK-recursive and mesh networks for network-on-chips, Proceedings of IEEE International Conference on Computer Design (ICCDí2006), October 1-3, 2006, San Jose, USA.

32.     H. Hashemi-Najafabadi, H. Sarbazi-Azad, An accurate combinatorial model for performance prediction of deterministic wormhole routing in torus multicomputer systems, Proceedings of IEEE International Conf. on Computer Design (IEEE ICCD'04), Oct. 25 - 29, 2004, San Jose, CA, USA, pp. 548-553.

33.     H. Hashemi-Najafabadi, H. Sarbazi-Azad, The effect of adaptivity on the performance of the OTIS-hypercube under different traffic patterns, Proceedings of IFIP International Conference on Network and Parallel Computing (IFIP NPC'2004), Lecture Notes in Computer Science, October 18-20, 2004, Wuhan, China, pp. 390-398 .

34.     A. Khonsari, H. Sarbazi-Azad, M. Ould-Khaoua, Analysis of true fully adaptive routing with software-based deadlock recovery, Proc. of International Conference on Parallel Processing (ICPP2001), 3-7 September, 2001, Valencia, Spain, pp. 393-400.

35.     H. Sarbazi-Azad, M. Ould-Khaoua, L.M. Mackenzie, S. Akl, Parallel Lagrange interpolation on the star, Proc. IEEE & ACM Int. Parallel & Distributed Processing Symposium (IPDPS'2000), IEEE Computer Society Press, Cancun, Mexico, May 1-5, 2000, pp. 777-782.

36.     H. Sarbazi-Azad, M. Ould-Khaoua, L.M. Mackenzie, An analytical model of fully-adaptive wormhole-routed k-ary n-cubes in the presence of hot-spot traffic, Proc. IEEE & ACM Int. Parallel & Distributed Processing Symposium (IPDPS'2000), IEEE Computer Society Press, Cancun, Mexico, May 1-5, 2000, pp. 605-610.